Douglas Clark, Butler Lampson and Kenneth Pier
Citation: IEEE Trans. Computers C-30, 10 (Oct. 1981), pp 715-732
Links: Abstract, Acrobat. Here is an HTML version created by OCR for the benefit of search engines; it is not meant for human consumption.
Email: blampson@microsoft.com. This paper is at http://www.research.microsoft.com.
Abstract:
The memory system of the Dorado, a compact high performance personal computer, has very high I/O bandwidth, a large paged virtual memory, a cache, and heavily pipelined control; this paper discusses all of these in detail. Relatively low speed I/O devices transfer single words to or from the cache; fast devices, such as a color video display, transferr directly to or the from main storage while the processor uses the cache. Virtual addresses are used in the cache and for all I/O transfers. The memory is controlled by a seven-stage pipeline, which can deliver a peak main-storage bandwidth of 533 million bits/s to service fast I/O devices and cache misses. Interesting problems of synchronization and scheduling in this pipeline are discussed. The paper concludes with some performance measurements that show, among other things, that the cache hit rate is over 99%.